Saige v1.0

A major percentage of all silicon-based designs go through multiple rounds of iterations and discussion between the RTL Digital Designer (person who rights the hardware description language, HDL) and Verification Engineer (person verifying functionality of the written HDL).

The fundamental verification methodology used in many design is Universal Verification Methodology. The language of interaction used in most of the cases is System Verilog.

However, this sector is itself going through a paradigm shift in they way things work. With the libraries such as Cocotb one can write verification code in Python.

Where we come in handy? We automate the process of generation of the Cocotb database for your RTL codes using Artificial Intelligence.

In one shot, we can understand your RTL code and generate (a) user-friendly verification code based on UVM (using pyuvm) and (b) Code coverage per use case

We offer this technology in multiple formats, one as a injectable add-on extension for VS Code and secondly, as a CLI version in which you can run the code library to generate your own code base.